
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:00:22 03/04/2012
-- Design Name:   Acc
-- Module Name:   C:/Xilinx92i/PROJECTAIC/tb_Acc.vhd
-- Project Name:  Procesador
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Acc
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_arith.all;

ENTITY tb_Acc_vhd IS
END tb_Acc_vhd;

ARCHITECTURE behavior OF tb_Acc_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT Acc
	PORT(
		alu_o : IN std_logic_vector(7 downto 0);
		clk : IN std_logic;
		load_acc_en : IN std_logic;          
		acc_o : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL load_acc_en :  std_logic := '1';
	SIGNAL alu_o :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL acc_o :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: Acc PORT MAP(
		alu_o => alu_o,
		acc_o => acc_o,
		clk => clk,
		load_acc_en => load_acc_en
	);


	clk <= not clk after 25 ns; -- periodo de 50 ns
	
	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		
		load_acc_en <= '0';
		alu_o <= conv_std_logic_vector(0,8);
		
		wait for 49 ns;
		
		alu_o <= conv_std_logic_vector(15,8);
		load_acc_en <= '1';	
		
		wait for 50 ns;
		
		assert(acc_o = conv_std_logic_vector(15,8))
						report "ERROR en carga del acumulador"
						severity FAILURE;
															
		load_acc_en <= '0';				
		alu_o <= conv_std_logic_vector(1,8);		
		
		wait for 50 ns;
		
		assert(acc_o = conv_std_logic_vector(15,8))
						report "ERROR en la desactivacion del enable del acumulador"
						severity FAILURE;
				
		
		load_acc_en <= '1';
		
		wait for 50 ns;
		
		assert(acc_o = conv_std_logic_vector(1,8))
						report "ERROR en carga del acumulador tras reactivacion enable"
						severity FAILURE;
				
		wait for 50 ns;
				
		report ("**********TESTS DE ACC SUPERADOS**********")
		severity NOTE;

	

		wait; -- will wait forever
	END PROCESS;

END;
